Truth Tables<\/span><\/h3>\nThe relationship between the input and output logic levels on a gate can be best illustrated using what is known as a \u201ctruth table\u201d.<\/span><\/p>\nA truth table is a table or chart that lists all of the possible input combinations and the resulting output logic level. \u00a0 Here is an example of a truth table:<\/span><\/p>\n\n\n\nA<\/span><\/td>\n | B<\/span><\/td>\n | Y<\/span><\/td>\n<\/tr>\n\n0<\/span><\/td>\n | 0<\/span><\/td>\n | 0<\/span><\/td>\n<\/tr>\n\n0<\/span><\/td>\n | 1<\/span><\/td>\n | 1<\/span><\/td>\n<\/tr>\n\n1<\/span><\/td>\n | 0<\/span><\/td>\n | 1<\/span><\/td>\n<\/tr>\n\n1<\/span><\/td>\n | 1<\/span><\/td>\n | 0<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n The inputs to our gate are labeled \u201cA\u201d and \u201cB\u201d, and the output is labeled \u201cY\u201d.<\/span><\/p>\n\n- When the inputs to our gate are both zero the output is zero.<\/span><\/li>\n
- When A=0 and B=1 the output is one.<\/span><\/li>\n
- When A=1 and B=0 the output is one.<\/span><\/li>\n
- When both inputs are one then the output is zero.<\/span><\/li>\n<\/ul>\n
By looking at the truth table you can determine the logic of the gate. Incidentally, the above truth table is for an \u201cExclusive OR\u201d gate.\u00a0 We\u2019ll examine that gate, and six others, right now.<\/span><\/p>\nNOT Gate<\/span><\/h3>\nThe NOT gate is the simplest of all the gates, it is also the only gate that only has one input.\u00a0 It is the first of the three elementary gates.<\/span><\/p>\n<\/p>\n This type of gate is sometimes referred to as an \u201cInverter\u201d, and from the truth table, it\u2019s easy to see why. The output of the NOT gate is the inverse of its input, in other words, it changes zeros into ones and ones into zeros.<\/span><\/p>\nThe boolean algebra description of the NOT gate is also shown, the line above the \u201cY\u201d indicates that the output is inverted.<\/span><\/p>\nWhile it may indeed be a simple gate the NOT gate is very useful, as inverting a digital signal is a common requirement when designing logic circuits.<\/span><\/p>\nAND Gate<\/span><\/h3>\nThe AND gate is the second of the three elementary gates, and its operation is illustrated below.<\/span><\/p>\n<\/p>\n As the truth table shows the AND gate has an output of zero unless all of its inputs are at one.\u00a0\u00a0<\/span><\/p>\nYou\u2019ll also note that the boolean symbol for an AND operation is a \u201cdot\u201d.<\/span><\/p>\nOR Gate<\/span><\/h3>\nThe third of the three elementary gates is the OR gate, illustrated below.<\/span><\/p>\n<\/p>\n The output of the OR gate is one whenever any of its inputs are set to one.<\/span><\/p>\nThe boolean symbol for the OR operation can be a bit confusing, as it is the same \u201c+\u201d symbol used for addition in standard mathematics.\u00a0 In boolean algebra 1 + 0 does indeed equal 1, but 1 + 1 also equals 1.<\/span><\/p>\nExclusive OR Gate<\/span><\/h3>\nThe remaining four gates are mainly derivatives of the first three.<\/span><\/p>\nThe Exclusive\u00a0 OR, or XOR gate, is shown here. Pay attention to its truth table, as it explains the operation best.<\/span><\/p>\n<\/p>\n As you can see the output of an Exclusive OR gate is set to one when only one input is set to one. Setting more than one input to one will cause the output to become zero.<\/span><\/p>\nThe boolean symbol for Exclusive OR is the \u201c+\u201d sign (a boolean OR) with a circle around it.<\/span><\/p>\nNAND Gate<\/span><\/h3>\nA NAND Gate is simply an AND gate with an inverted output.<\/span><\/p>\n<\/p>\n In this case, the operation is exactly opposite to that of the AND gate. The output is one unless all of the inputs are one.<\/span><\/p>\nThis is a very common gate, and in a moment I\u2019ll explain why.<\/span><\/p>\nNOR Gate<\/span><\/h3>\nAs with the NAND gate, a NOR gate is just an OR gate with an inverted output.<\/span><\/p>\n<\/p>\n The only situation in which a NOR gate will output a one is if both of the inputs are zero.<\/span><\/p>\nNote the boolean formula for a NOR gate uses a line to indicate an inversion.<\/span><\/p>\nExclusive NOR Gate<\/span><\/h3>\nYou guessed it, and Exclusive NOR gate is an inverted Exclusive OR gate!<\/span><\/p>\n<\/p>\n You\u2019ll sometimes see this written as an \u201cXNOR\u201d gate. Its output is a one providing all of the inputs are the same, either all zeros or all ones. Any other combination results in an output of zero.<\/span><\/p>\nNAND Gates as \u201cUniversal\u201d Gates<\/span><\/h3>\nAs we just saw, a NAND gate is essentially an AND gate with an inverted output. In fact, you could easily construct a NAND gate by combining an AND gate and an Inverter, as shown here.<\/span><\/p>\n<\/p>\n As it turns out NAND gates are about the most common gate around. This is because you can create any of the other basic logic gates using a combination of NAND gates.<\/span><\/p>\nTo make an inverter or NOT gate you can just tie all of the inputs of a NAND gate together (this same trick will work with a NOR gate as well).<\/span><\/p>\n<\/p>\n Now since you can make an inverter with a NAND gate it becomes easy to create an AND gate. Just invert the output of another NAND gate, as shown here.<\/span><\/p>\n<\/p>\n With three NAND gates, we can make an OR gate.<\/span><\/p>\n<\/p>\n And, of course, if we invert the output of that we\u2019ll have a NOR gate.<\/span><\/p>\n<\/p>\n Some chip designers only use NAND gates and create all of the other logic gates with them. It may seem wasteful, but with chip densities being what they are these days it\u2019s not a big deal, and the chip is easier to design if all of the gates are the same.<\/span><\/p>\nBuffers & Schmitt Triggers<\/span><\/h2>\nThere are a few other logic components you should know about. These are not really \u201cgates\u201d, rather they are elements that either enhance the operation of the gates or allow them to be interconnected in the \u201dreal world\u201d where you have to worry about things like maximum current capabilities and noisy logic signals.<\/span><\/p>\nBuffers<\/span><\/h3>\nAt first glance, the buffer seems like the most useless \u201cgate\u201d there is. That\u2019s because logically it does nothing at all!<\/span><\/p>\n<\/p>\n The input to the buffer equals its output. And while that seems about as useful as just using a piece of wire, it actually has a very good use.<\/span><\/p>\nIn the \u201creal world\u201d that I referred to, a logic gate has a finite number of other gates it can drive before the current demands are too great.\u00a0 The number of gates a chip can drive is referred to as its \u201cfan-out\u201d. So a gate with a fan-out of 2 can only drive two other gates.<\/span><\/p>\nBuffers typically have a higher fan-out and can therefore be used to drive several other gates.<\/span><\/p>\nIn the following illustration, a portion of a logic circuit is shown. The buffer is driving the inputs on the XNOR, NOT, and AND gates, as the NAND gate is not capable of doing that itself.<\/span><\/p>\n<\/p>\n In addition, buffers can be used to drive high-current devices, such as LEDs. More on that in a bit.<\/span><\/p>\nTri-state Buffer<\/span><\/h3>\nA TRi-state buffer is illustrated here. As you can see, it\u2019s essentially a buffer with another input.<\/span><\/p>\n<\/p>\n The first thing you likely will notice is the odd truth table, it has two outputs labeled \u201cH\u201d instead of one or zero.\u00a0 What\u2019s up with that?<\/span><\/p>\nThe extra input, labeled \u201cE\u201d, is an Enable line. It essentially lets you turn the buffer on or off.<\/span><\/p>\nWhen the buffer is on or enabled,\u00a0 it essentially acts just like a normal buffer, allowing the data to pass through unaltered.<\/span><\/p>\nBut when the buffer is off, or disabled, it puts the output into a high-impedance state. In other words, it is disconnected, there is no output at all. This is very different from just a zero.<\/span><\/p>\nTri-state buffers are used extensively when driving a common data bus. Only one component at a time can drive the data bus, so by employing tri-state buffers we can ensure that.<\/span><\/p>\nThis can be illustrated using three simple diagrams.\u00a0<\/span><\/p>\n<\/p>\n The first diagram shows our circuit. It has multiple inputs in two sections. The top section uses a NAND gate, the bottom one uses an Exclusive NOR (XNOR) gate.\u00a0 Both these sections feed a tri-state buffer, and the output of both buffers are connected together and fed into the input of a standard buffer.<\/span><\/p>\nIn the first illustration both buffers are disabled, so neither section sends its output to the final buffer.<\/span><\/p>\n<\/p>\n In the second illustration, we have enabled the top tri-state buffer.\u00a0 The output of the NAND gate is now allowed to pass to the input of the output buffer.<\/span><\/p>\n<\/p>\n In the final illustration, the lower tri-state buffer is enabled, while the top one is disabled. The output of the XNOR gate is not presented to the input of the final buffer.<\/span><\/p>\nOf course, it is imperative that you never enable both of the tri-state buffers simultaneously. Doing that would send both signals to the output buffer, an undesirable situation both logically and electrically.<\/span><\/p>\nIncidentally, there are other gates available that have tri-state outputs, essentially they are a fusion of a gate and a tri-state buffer.<\/span><\/p>\nSchmitt Triggers<\/span><\/h3>\nThe Schmitt Trigger is not really a gate, although I have shown it as a NOT gate.<\/span><\/p>\n<\/p>\n As a gate, the Schmitt Trigger operates like any other. The special property of this device lies within its electrical characteristics.<\/span><\/p>\nBack in that \u201creal world” which I mentioned previously electrical signals are not always perfect. Connections made with thin PCB traces running next to other connections in an electrically \u201cnoisy\u201d environment can result in degraded signals.<\/span><\/p>\nA Schmitt Trigger can \u201cclean up\u201d this signal. Internally a Schmitt Trigger contains a couple of comparators, devices that sense whether a voltage is above or below a specified level.\u00a0 These comparators treat every signal above a specified threshold as a one, and signals below that as a zero.<\/span><\/p>\nEvery basic gate is also available as a Schmitt Trigger.<\/span><\/p>\nIn the following illustration, we have a NAND gate driving a buffer using a long line, which is picking up electrical noise.\u00a0 This results in an output from the buffer that doesn\u2019t match the output of the NAND gate, a situation to be avoided at all costs.<\/span><\/p>\n<\/p>\n If we replace the buffer with a buffer that contains a Schmitt Trigger then the situation is resolved. Although the signal still gets degraded the Schmitt Trigger cleans it up and restores it back to its original condition.<\/span><\/p>\n<\/p>\n A handy component indeed, at least in the \u201creal world\u201d!<\/span><\/p>\nLogic Gate Families<\/span><\/h2>\nThere are thousands of logic chips, and they can be divided into groups based upon their underlying technology.\u00a0 These groups are referred to as \u201clogic families\u201d.<\/span><\/p>\n<\/p>\n The original logic chips were constructed over half a century ago using bipolar technology. There were many bipolar-based families:<\/span><\/p>\n\n- DL <\/b>– Diode Logic<\/span><\/li>\n
- RTL<\/b> – Resistor-Transistor Logic<\/span><\/li>\n
- DTL<\/b> – Diode-Transistor Logic<\/span><\/li>\n
- TTL<\/b> – Transistor-Transistor Logic<\/span><\/li>\n<\/ul>\n
Of these only TTL chips remain today. The digital \u201cbreakthrough products\u201d of the 1960s and 1970s were all built with TTL chips, for a long time they were the dominant logic chip family.<\/span><\/p>\nBut TTL chips were not perfect. While they are fast and reliable they also had a couple of big drawbacks.<\/span><\/p>\nOne issue was that they consumed a lot of current due to their bipolar transistor design, so battery-powered equipment was not usually possible (and remember, battery technology in the 1960s was not what it is today).\u00a0\u00a0<\/span><\/p>\nAlso, they required a strictly regulated 5-volt power supply, in fact, they are what gave rise to 5-volts becoming the \u201cstandard\u201d logic voltage for a long time.\u00a0 And, in turn, they made the 7805 linear voltage regulator a very popular component!<\/span><\/p>\nOther families were created using Metal Oxide Semiconductors, or MOS devices.\u00a0<\/span><\/p>\n\n- PMOS<\/b> – Positive Metal Oxide Semiconductor.\u00a0<\/span><\/li>\n
- NMOS<\/b> – Negative Metal Oxide Semiconductor.\u00a0<\/span><\/li>\n
- CMOS<\/b> – Complementary Metal Oxide Semiconductor.\u00a0<\/span><\/li>\n<\/ul>\n
All of these technologies are still in use today, with CMOS logic chip families being very popular for battery-powered devices. CMOS chips consume minimal power, have large fan-out capabilities, and work on a wide range of power supply voltages.<\/span><\/p>\nThere are also families based upon BiMOS, a fusion of bipolar and MOS technology. Bipolar devices still have speed advantages over MOS, so combining these on a single chip allows for the best of both worlds.<\/span><\/p>\n | | | | |